job requires 5+ years of applicable ASIC verification experience supported by a ... Experience is preferable in the following languages: - C/C++, - Vera - SystemVerilog... more

design, RTL level VHDL-based logic design, verification/validation, timing analysis, ... industries. Desired Skills: -Functional Verification experience using Vera or System... more

The FAE should have strong background in VERIFICATION and Verification Methodologies ... methodologies with emphasis placed on the verification and design process. more

modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. Write verification test plans. Run synthesis,... more

- ASIC - RTL - SAS - SATA - Verilog - Vera Verification Engineer - ASIC - RTL - ... Verilog, Vera, C/C++ , Storage, System C, Vera, System Verilog Verification Engineer -... more

activities in support of creating the Vera Bradley 'experience through exceptional ... awareness and loyalty * Communicate the Vera Bradley brand aesthetic, philosophy and... more

job requires 5+ years of applicable ASIC verification experience supported by a ... Experience is preferable in the following languages: - C/C++, - Vera - SystemVerilog... more

design, RTL level VHDL-based logic design, verification/validation, timing analysis, ... industries. Desired Skills: -Functional Verification experience using Vera or System... more

job requires 5+ years of applicable ASIC verification experience supported by a ... Experience is preferable in the following languages: - C/C++, - Vera - SystemVerilog... more

design, RTL level VHDL-based logic design, verification/validation, timing analysis, ... industries. Desired Skills: * Functional Verification experience using Vera or System... more

modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. . Write verification test plans. . Run synthesis,... more

? Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). ? Familiar with FPGA simulation tools (such as Aldec, Mentor,... more

* Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). * Familiar with FPGA simulation tools (such as Aldec, Mentor,... more

verification environments using Hardware Verification Languages such as ... important verification concepts related to verification methodology and coverage... more

Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). Familiar with FPGA simulation tools (such as Aldec, Mentor,... more

- Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). - Familiar with FPGA simulation tools (such as Aldec, Mentor,... more

The FAE should have strong background in VERIFICATION and Verification Methodologies ... methodologies with emphasis placed on the verification and design process. more

Experience in simulation based FPGA/ASIC verification methodologies using advanced ... Vera, e, etc.).* Familiar with FPGA simulation tools (such as Aldec, Mentor,... more

and implementing testplans, developing Vera/SystemVerilog tests and checkers, ... flows and methodologies - Has hand-on verification experience of network traffic... more

Title: Block Level Verification EngineerDuration: 04 Month ContractLocation: San ... with verification only. Do not want to see design engineers only verification... more

modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. Write verification test plans. Run synthesis,... more

Oriented Verification languages such as Vera, Specman or System Verilog) required. ... test plans, generating and tracking verification schedules, simulation... more

Drive Organization Name Microprocessor Verification Engineering Department ... such as SystemVerilog, Verilog and Vera. 5 years experience in verification... more

of IP integration. ?Experience with Verilog simulation Synopsys DesignCompiler, Synopsys ... knowledge of VHDL, SystemVerilog, Specman, Vera, System C ?Knowledge of protocols such... more

Verification Engineer - ASIC - RTL - SAS - SATA - Verilog - Vera Verification ... - ASIC - RTL - SAS - SATA - Verilog - Vera - C/C++ - System Verilog Verification... more

system modeling and simulation- Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera.* Write verification test plans.* Run synthesis,... more

and implementing testplans, developing Vera/SystemVerilog tests and checkers, ... flows and methodologies- Has hand-on verification experience of network traffic... more

definition to design and verification. Verification engineers with ... "verification engineers", system verilog, verilog, vmm, ovm, perl, vera,... more

Looking for a Block Level Verification Engineer. Need to have experience with Vera and RVM. Need to have 10-20 years of experience with verification only. more

Description:Looking for a Block Level Verification Engineer. Need to have experience ... with verification only. Do not want to see design engineers only verification... more

definition to design and verification. Verification engineers with ... "verification engineers", system verilog, verilog, vmm, ovm, perl, vera,... more

modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. Write verification test plans. Run synthesis,... more

possible problems; propose new flows using verification knowledge, best practices and ... using both block level and chip level verification expertise. Highly independent,... more

* Experience in gate level simulations, performance modeling and HW/SW co-verification a ... * Requires fluency in Verilog, Vera/System Verilog, C/C++ and/or System C... more

Category : Engineering Position Type : Verification Shift : 1st shift - ... and implementing testplans, developing Vera/SystemVerilog tests and checkers,... more

such as SystemVerilog, Verilog and Vera. 5 years experience in verification ... scripting languages Waveform viewing and simulation debugging Post-silicon bringup... more

and implementing testplans, developing Vera/SystemVerilog tests and checkers, ... flows and methodologies - Has hand-on verification experience of network traffic... more

Oriented Verification languages such as Vera, Specman or System Verilog) required. ... test plans, generating and tracking verification schedules, simulation... more

system modeling and simulation- Development/simulation of RTL hardware implementations ... like System Verilog or System C or Vera.. Write verification test plans.. Run... more

with 5-7 years of experiences in verification, and modeling- VERA or ... Verilog Design/Verification Digital Chip: Vera Design/Verification Digital Chip: NC... more

Title t('12') Switch Verification Engineer t('5') Location t('12') US-Santa ... Individual contributor responsible for the verification of high performance... more

HVLs(VERA) knowledge required Maintaining cost reduction and quality improvement ... verification methodologies, test planning, verification environment architectures and... more

like System Verilog or System C or Vera. - Able to write verification test ... synthesis, static timing analysis, formal verification. - Understanding of timing... more

HVLs(VERA) knowledge required Maintaining cost reduction and quality improvement ... verification methodologies, test planning, verification environment architectures and... more

Individual contributor responsible for the verification of high performance ... of direct experience in microprocessor verification. Knowledge of Sparc Assembly... more

Title t('12') Hardware Verification Engineer t('5') Location t('12') US-Santa ... - BS / MS (preferred) with 5-7 years of experiences in verification, and modeling - VERA... more

utilizing constraint based random verification methodologies and industry ... verification. Perform test development, simulation, debugging, system bring up and... more

like System Verilog or System C or Vera. - Able to write verification test ... synthesis, static timing analysis, formal verification. - Understanding of timing... more

of Serdes macros and clusters; developing verification checkers, monitors, functional ... - BS / MS (preferred) with 5-7 years of experiences in verification, and modeling - VERA... more

experience in creating Coverage Driven Verification environments utilizing ... Verification Engineer or Design Engineer or Verification AE. Experience in leading... more