vera verification simulation jobs

for motivated and innovative design verification engineer to be part of Marvell's ... Test Bench development, simulations, design verification and debug- Familiarity with... more

excellent understanding of SOC integration, simulation and laboratory troubleshooting. ... Verilog design, and constrained random verification tools such as Vera or Specman.... more

Verification Engineer (Member Technical Staff) Looking for an ASIC verification ... products. Responsibilities include verification of ASICs and systems for... more

verification.. Strong knowledge of HVLs(VERA), HDLs(Verilog/VHDL/SystemVerilog), ... RTL simulation (ModelSim, VCS, Vera), Formal verification techniques (e.g.... more

Implement the verification environment and methodology for the world's ... Utilize dynamic simulation, formal verification, emulation, and code coverage-... more

verification environment. Write verification test plans. Execute code ... Extensive experience with SystemVerilog or Vera is required... more

of verification projects using high level verification languages Work very closely ... coverage Experience in architecting verification environments and writing test... more

of verification projects using high level verification languages Work very closely ... coverage Experience in architecting verification environments and writing test... more

and implement verification IP for Ethernetswitches, routers, and SOC ... level verification language (SystemVerilog, Vera, Specman). 4. Solid understanding of... more

verification. Prior experience doing simulation based verification of small to ... CE, or CSADDITIONAL COURSE WORK:Design Verification EngineeringSun Microsystems... more

methodology and who can handle system verification tasks very efficiently. ... Expertise in verilog, SystemVerilog/VERA (SV, VMM/RVM) Good experience in perl,... more

System Verilog, SystemC, Vera, etc) ... (i.e., SystemVerilog, SystemC, Verilog, e, Vera etc) l Various verification methodology(s) l regression test-suite dvlpmt l Creation... more

Position Description:Looking for motivated and innovative design verification engineer to ... Test Bench development, simulations, design verification and debug- Familiarity with... more

verification. Prior experience doing simulation based verification of small to ... CE, or CSADDITIONAL COURSE WORK:Design Verification EngineeringSun Microsystems... more

coverage;- Support for relevant FPGA based verification Qualifications(Required Skills ... coverage, etc.- Hand-on experience with RTL verification with Specman or Vera is... more

Vera tests and checkers, creating reusable verification components, and debugging ... functional team members, and enhance the verification methodology. - This... more

Verification; Verilog; Verilog/VHDL RTL Verification Engineer Assist in RTL ... RTL simulator. Experience in Specman "e" verification language or Vera. Knowledge of... more

in RTL/Behavioral modeling in Verilog EDA Simulation tools (VCS,NCSIM) * Working ... languages including C/C++ * Experienced in Verification of Layer 2 (Ethernet/WLAN)... more

Vera and/or PSL and Assertion-Based Verification techniques.** Experience in ... random directed testing, formal verification and simulation... more

automated, coverage-driven SOC verification environment, where reuse is of high importance. There will be testbench ... across simulation, emulation and silicon bringup 3... more

customer wins. -Driving adoption of verification products in existing ... on verification methodologies/flows OVM, E, Vera, Specman, VMM, RMM). ,oPrior experience... more

are second to none. Responsible for verification of hard disk controller ... tests. Experience with advanced random verification methodologies is highly... more

• At least 4-10+ years experience ASIC verification ... • Experience in gate level simulations, performance modeling and HW/SW co-verification... more

to none. Responsible for cosimulation and verification of disc controller, host ... System Verilog). Experience with advanced verification languages (Vera, Specman) is... more

Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate ... verification environments, modeling and co-simulation, testvector generation, at the IP... more

Juniper is growing! We are looking for ASIC verification engineers to work in a dynamic ... Responsibilities include architecture development and modeling, verification of ASIC and... more

responsible for designing and developing verification environment components; ... ASIC verification experience should include use of modern verification techniques,... more

ASICs in the area of logic design and verification of -- packet processing ... * strength in digital logic design, verification. knowledge of HDL such as... more

and implementation of software based verification environments. The candidate ... language (Specman/e) to create advanced verification environments. They should be... more

Participate in the verification of next-generation high-performance FPGA ... testing, system level verification ? Fluent in Verilog, Vera/Specman, C, C++,... more

Create Vera/SystemVerilog test benches and test cases for hardware verification ... and simulation techniques, including HVLs (vera/System Verilog) and Verilog. The... more

LEAD VERIFICATION ENGINEER Responsibilities: Architect the verification environment ... Vera or Specman ?e? Worked with multiple verification development cycles Demonstrate... more

Principle Microprocessor Design Verification Engineers!! Join an elite design ... Knowledge in verification methodologies from concept to working silicon ... more

include: • Develop functional test/verification plans, verification modules, ... programming skills • System Verilog, Vera, E, or assertion based verification... more

perl/shell scripting, and VHDL for simulation and synthesis is preferred. Must ... in a fast-paced environment. Experience with Vera and lab test equipment are... more

Description:Architect and implement verification IP for Ethernetswitches, ... level verification language (SystemVerilog, Vera, Specman). 4. Solid understanding of... more

activities including generation of verification plans, generation of ... methods including constrained random verification methods and functional coverage... more

include concept development, requirements, verification plan, chip architecture, detail ... design, back-annotated timing Gate-level Simulation, Static Timing Analysis,... more

Principal Verification Engineer Verification The industry?s most respected ... Vera tests and checkers, creating reusable verification components, and debugging... more

knowledge of ASIC design verification flows and methodologies is ... is strongly preferred.Familiarity with Vera, C++/Specman/SystemC or OOP is highly... more

CA Job Description: Responsible for verification of IP functionality and ... verification test plans ? System Verilog, Vera, or Specman experience strongly desired... more

5-10 years Requirements: * Fullchip verification testbench and environment ... specs for components and modules in the verification environment (test benches,... more

Please contact Zafar at 510-402-4799 Or mail me at zafar@apninc.com*****************************************************Need strong Vera/RVM skills Need strong Vera/RVM skills more

? Experience in SystemVerilog, Specman, or VERA ? Knowledge of interface protocols ... of professional experience in Verification of ASIC/SoCs, or CAD Tool development... more

Must have a strong background in verification and verification methodologies ... ? Must understand multiple HDL methodologies with emphasis placed on the verification and... more

Must have a strong background in verification and verification methodologies ... ? Must understand multiple HDL methodologies with emphasis placed on the verification and... more

Experience may include: ASIC design and/or verification experience, ideally doing some ... design, ASIC simulation, ASIC post-silicon verification, ASIC microcode, formal... more

responsible for designing and developing verification environment components; ... ASIC verification experience should include use of modern verification techniques,... more

modeling and simulation - Development/simulation of RTL hardware implementations ... like System Verilog or System C or Vera. . Write verification test plans. . Run... more

with Vera / Specman / VerilogUnix / C++5 years experience Verification, Specman, Vera,... more