vera verification simulation jobs
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| Mar 20 | Design Verification Engineers | New Nyc Opportunity! | New York, NY |
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Design Verification Engineers Location: NYC Salary: 100K plus/ Depends on Experience ... with verification test languages such as Vera. Knowledge of VHDL or Verilog language... more |
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| Mar 19 | Verification Engineer, RTP | Cisco Systems | North Carolina |
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job requires 5+ years of applicable ASIC verification experience supported by a ... Experience is preferable in the following languages: - C/C++, - Vera - SystemVerilog... more |
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| Mar 19 | Engineer, Principal Design | Broadcom | Austin, TX |
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modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. Write verification test plans. Run synthesis,... more |
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| Mar 19 | Digital Design Section Head | Raytheon | Goleta, CA |
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design, RTL level VHDL-based logic design, verification/validation, timing analysis, ... industries. Desired Skills: -Functional Verification experience using Vera or System... more |
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| Mar 18 | Design Verification Engineer ASIC Large Scale systems | New Jersey | |
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Vera, SystemVerilog, First-Pass, Silicon Success, Complex ASIC Design Verification ... of testing, functional coverage, chip verification - Intermediate to expert level... more |
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| Mar 18 | Field Application Engineers (FAE) [Verification EXp] | Inmata Solutions, Inc. | Mountain View, CA | Sunnyvale, CA |
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The FAE should have strong background in VERIFICATION and Verification Methodologies ... methodologies with emphasis placed on the verification and design process. more |
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| Mar 18 | Engineer, Principal Design | Broadcom | Austin, TX |
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modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. . Write verification test plans. . Run synthesis,... more |
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| Mar 18 | Engineer, Principal Design | Broadcom | Austin, TX |
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modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. Write verification test plans. Run synthesis,... more |
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| Mar 17 | Verification Engineers | Koa Networks | San Jose, CA |
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Verification Engineers Skills: programming skills SystemVerilog Vera Specman ... Vera, or Specman. ** Familiar with verification reuse methodologies such as VMM... more |
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| Mar 17 | Verification Engineer ASIC RTL SAS SATA Verilog Vera | California | |
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- ASIC - RTL - SAS - SATA - Verilog - Vera Verification Engineer - ASIC - RTL - ... Verilog, Vera, C/C++ , Storage, System C, Vera, System Verilog Verification Engineer -... more |
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| Mar 17 | Verification Engineers | Koa Networks | San Jose, CA |
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Verification Engineers Skills: programming skills SystemVerilog Vera Specman ... Vera, or Specman. ** Familiar with verification reuse methodologies such as VMM... more |
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| Mar 17 | Assistant Store Manager - Operations | Vera Bradley | Wrentham, MA |
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activities in support of creating the Vera Bradley 'experience through exceptional ... awareness and loyalty * Communicate the Vera Bradley brand aesthetic, philosophy and... more |
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| Mar 17 | Verification Engineer - ASIC - RTL - SAS - SATA - Verilog - Vera - C/C++ - System Verilog | Cybercoders | Irvine, CA |
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Verification Engineer - ASIC - RTL - SAS - SATA - Verilog - Vera - C/C++ - System Verilog ... C, Vera, System Verilog Job Description Verification Engineer - ASIC - RTL - SAS -... more |
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| Mar 17 | Hardware Engineer | Cisco Systems | San Jose, CA |
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job requires 5+ years of applicable ASIC verification experience supported by a ... Experience is preferable in the following languages: - C/C++, - Vera - SystemVerilog... more |
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| Mar 17 | Hardware Engineer | Cisco Systems | North Carolina |
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job requires 5+ years of applicable ASIC verification experience supported by a ... Experience is preferable in the following languages: - C/C++, - Vera - SystemVerilog... more |
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| Mar 17 | Digital Design Section Head | Raytheon | Santa Barbara, CA |
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design, RTL level VHDL-based logic design, verification/validation, timing analysis, ... industries. Desired Skills: -Functional Verification experience using Vera or System... more |
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| Mar 17 | Hardware Engineer | Cisco Systems | San Jose, CA |
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job requires 5+ years of applicable ASIC verification experience supported by a ... Experience is preferable in the following languages: - C/C++, - Vera - SystemVerilog... more |
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| Mar 17 | Hardware Engineer | Cisco Systems | North Carolina |
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job requires 5+ years of applicable ASIC verification experience supported by a ... Experience is preferable in the following languages: - C/C++, - Vera - SystemVerilog... more |
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| Mar 17 | Digital Design Section Head | Raytheon | Goleta, CA |
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design, RTL level VHDL-based logic design, verification/validation, timing analysis, ... Desired Skills: -Functional Verification experience using Vera or System... more |
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| Mar 16 | Digital Design Section Head | Raytheon | Goleta, CA |
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design, RTL level VHDL-based logic design, verification/validation, timing analysis, ... industries. Desired Skills: * Functional Verification experience using Vera or System... more |
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| Mar 15 | Design Verification Engineer - ASIC - Large Scale systems | Cybercoders | New York, NY |
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Design Verification Engineer - ASIC - Large Scale systems - C/C++ - Vera - ... of testing, functional coverage, chip verification - Intermediate to expert level... more |
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| Mar 15 | Engineer, Principal Design | Broadcom | Austin, TX |
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modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. . Write verification test plans. . Run synthesis,... more |
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| Mar 13 | Principal Engineer | Seagate Technology | Longmont, CO |
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* Be responsible for coordinating verification activities and test plan ... with current object-oriented hardware verification methodologies such as Vera/RVM... more |
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| Mar 13 | Principal FPGA Engineer | Westinghouse Electric Company | Cranberry Township, PA |
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? Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). ? Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 13 | Senior FPGA Engineer | Westinghouse Electric Company | Cranberry Township, PA |
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? Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). ? Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 12 | Senior FPGA Engineer | Westinghouse Electric | Cranberry Township, PA |
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* Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). * Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 12 | Principal FPGA Engineer | Westinghouse Electric | Cranberry Township, PA |
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* Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). * Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 12 | Functional Verifcation / OVM Soluti... | CAE Recruiters | San Jose, CA |
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verification environments using Hardware Verification Languages such as ... important verification concepts related to verification methodology and coverage... more |
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| Mar 11 | Principal FPGA Engineer | Westinghouse Electric Company | Cranberry Twp, PA |
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Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 11 | Senior FPGA Engineer | Westinghouse Electric Company | Cranberry Twp, PA |
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Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 11 | Verification Engineer - ASIC - RTL ... | Cybercoders | Irvine, CA |
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Verification Engineer - ASIC - RTL - SAS - SATA - Verilog - Vera Job in Irvine 92602, California US a... more |
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| Mar 11 | Principal FPGA Engineer | Westinghouse Electric Company | Pittsburgh, PA |
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- Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). - Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 11 | Senior FPGA Engineer | Westinghouse Electric Company | Pittsburgh, PA |
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- Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). - Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 10 | Field Application Engineers (FAE) [Verification EXp] | Inmata Solutions | Mountain View, CA |
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The FAE should have strong background in VERIFICATION and Verification Methodologies ... methodologies with emphasis placed on the verification and design process. more |
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| Mar 10 | Senior FPGA Engineer | Westinghouse Electric Company | Cranberry Township, PA |
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Experience in simulation based FPGA/ASIC verification methodologies using advanced ... Vera, e, etc.).* Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 10 | Principal FPGA Engineer | Westinghouse Electric Company | Cranberry Township, PA |
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Experience in simulation based FPGA/ASIC verification methodologies using advanced ... Vera, e, etc.).* Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 09 | Principal FPGA Engineer | Westinghouse Electric Company | Pennsylvania |
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? Experience in simulation based FPGA/ASIC verification methodologies using ... Vera, e, etc.). ? Familiar with FPGA simulation tools (such as Aldec, Mentor,... more |
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| Mar 09 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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and implementing testplans, developing Vera/SystemVerilog tests and checkers, ... flows and methodologies - Has hand-on verification experience of network traffic... more |
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| Mar 08 | Block Level Verification Engineer - Local Candidates Only | Active Soft | San Jose, CA |
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Description: Looking for a Block Level Verification Engineer. Need to have experience ... Do not want to see design engineers only verification engineers.Job Type:... more |
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| Mar 08 | Looking for a Block Level Verification Engineer. | Vaktech | San Jose, CA |
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Title: Block Level Verification EngineerDuration: 04 Month ContractLocation: San ... with verification only. Do not want to see design engineers only verification... more |
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| Mar 08 | Assistant Store Manager - Operations | Vera Bradley Designs | Wrentham, MA |
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activities in support of creating the Vera Bradley 'experience through exceptional ... that communicate and represent the Vera Bradley philosophyAssist in the... more |
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| Mar 08 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. Write verification test plans. Run synthesis,... more |
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| Mar 07 | ASIC Design and Verification Engineer | Terran Systems | San Jose, CA |
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of overall verification strategy, simulation environment, coverage ... Vera verification environment, common RTL simulation & verification tools- System... more |
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| Mar 07 | ASIC Verification Sr. Staff | Conexant | Waltham, MA |
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Oriented Verification languages such as Vera, Specman or System Verilog) required. ... test plans, generating and tracking verification schedules, simulation... more |
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| Mar 07 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. Write verification test plans. Run synthesis,... more |
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| Mar 07 | Hardware Developer 4 | Oracle | Burlington, MA |
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Drive Organization Name Microprocessor Verification Engineering Department ... such as SystemVerilog, Verilog and Vera. 5 years experience in verification... more |
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| Mar 06 | ASIC Functional Verification Architect | CAE Recruiters | San Jose, CA |
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is looking for an architect leveldesign verification and EDA Tools engineer to work ... of IP integration. ?Experience with Verilog simulation Synopsys DesignCompiler, Synopsys... more |
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| Mar 06 | ASIC Functional Verification Architect | CAE Recruiters | San Jose, CA |
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of IP integration. ?Experience with Verilog simulation Synopsys DesignCompiler, Synopsys ... knowledge of VHDL, SystemVerilog, Specman, Vera, System C ?Knowledge of protocols such... more |
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| Mar 06 | Verification Engineer | Cybercoders | Irvine, CA |
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Verification Engineer - ASIC - RTL - SAS - SATA - Verilog - Vera Verification ... - ASIC - RTL - SAS - SATA - Verilog - Vera - C/C++ - System Verilog Verification... more |
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| Mar 06 | Verification Engineer | Cybercoders | Newport Beach, CA |
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Verification Engineer - ASIC - RTL - SAS - SATA - Verilog - Vera Verification ... - ASIC - RTL - SAS - SATA - Verilog - Vera - C/C++ - System Verilog Verification... more |
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| Mar 06 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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system modeling and simulation- Development/simulation of RTL hardware implementations ... like System Verilog or System C or Vera.* Write verification test plans.* Run... more |
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| Mar 06 | Engineer, Principal Design | Broadcom | Austin, TX |
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system modeling and simulation- Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera.* Write verification test plans.* Run synthesis,... more |
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| Mar 06 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. Write verification test plans. Run synthesis,... more |
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| Mar 06 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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and implementing testplans, developing Vera/SystemVerilog tests and checkers, ... flows and methodologies- Has hand-on verification experience of network traffic... more |
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| Mar 05 | ASIC Design and Verification Engineer | Terran Systems | San Jose, CA |
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Verification Requirements: Position Overview Prospective candidate will design ... of overall verification strategy, simulation environment, coverage methodology... more |
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| Mar 05 | ASIC Verification Engineer | Koa Networks | San Jose, CA |
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definition to design and verification. Verification engineers with ... "verification engineers", system verilog, verilog, vmm, ovm, perl, vera,... more |
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| Mar 05 | Block Level Verification Engineer | Agile Enterprise Solutions | San Jose, CA |
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Description:Looking for a Block Level Verification Engineer. Need to have ... with Vera and RVM. Need to have 10-20 years of experience with verification... more |
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| Mar 05 | Block Level Verification Engineer | Protingent | San Jose, CA |
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Looking for a Block Level Verification Engineer. Need to have experience with Vera and RVM. Need to have 10-20 years of experience with verification only. more |
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| Mar 05 | Block Level Verification Engineer | Agile Enterprise Solutions | San Jose, CA |
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Candidates OnlyLooking for a Block Level Verification EngineerNeed to have experience ... with verification onlyDo not want to see design engineers only verification... more |
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| Mar 05 | Block Level Verification Engineer - Local Candidates Only | Active Soft | San Jose, CA |
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Description:Looking for a Block Level Verification Engineer. Need to have experience ... with verification only. Do not want to see design engineers only verification... more |
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| Mar 04 | Design Verification Engineer | QUALCOMM | Santa Clara, CA |
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levels - seeking engineers with a range of verification experience. * Solid OOPs ... testing * Strong working knowledge of HVLs: VERA/e-Specman * Verilog or VHDL, C/C++,... more |
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| Mar 03 | ASIC Verification Engineer | Koa Networks | San Jose, CA |
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definition to design and verification. Verification engineers with ... "verification engineers", system verilog, verilog, vmm, ovm, perl, vera,... more |
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| Mar 03 | Assistant Store Manager - Operations (2010050) | Vera Bradley | Wrentham, MA |
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activities in support of creating the Vera Bradley 'experience through exceptional ... that communicate and represent the Vera Bradley philosophy Assist in the... more |
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| Mar 03 | Senior Staff IC Design Engineer | Broadcom | Irvine, CA |
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modeling and simulation - Development/simulation of RTL hardware implementations ... System Verilog or System C or Vera. Write verification test plans. Run synthesis,... more |
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| Mar 02 | Assistant Store Manager - Operations | Vera Bradley | Wrentham, MA |
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activities in support of creating the Vera Bradley 'experience through exceptional ... awareness and loyalty * Communicate the Vera Bradley brand aesthetic, philosophy and... more |
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| Mar 02 | Sr. Staff IC Design Engineer | Xilinx | San Jose, CA |
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possible problems; propose new flows using verification knowledge, best practices and ... using both block level and chip level verification expertise. Highly independent,... more |
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| Mar 02 | Hardware Developer 4 | Oracle | Santa Clara, CA |
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t('5') Organization Name t('12') Design Verification t('5') Department Description ... verification IP. Hands on experience with Vera/NTB/SystemVerilog or similar language... more |
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| Mar 01 | Principal ASIC Verification Engineer | Ericsson | San Jose, CA |
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* Experience in gate level simulations, performance modeling and HW/SW co-verification a ... * Requires fluency in Verilog, Vera/System Verilog, C/C++ and/or System C... more |
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| Mar 01 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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Category : Engineering Position Type : Verification Shift : 1st shift - ... and implementing testplans, developing Vera/SystemVerilog tests and checkers,... more |
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| Mar 01 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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Category : Engineering Position Type : Verification Shift : 1st shift - ... and implementing testplans, developing Vera/SystemVerilog tests and checkers,... more |
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| Feb 28 | Hardware Developer 4 | Oracle | Spring, TX |
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verification IP. Hands on experience with Vera/NTB/SystemVerilog or similar language ... Technology -> Semiconductor Design/Verification Engineer Design/Verification... more |
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| Feb 26 | Hardware Developer 4 | Oracle | Burlington, MA |
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such as SystemVerilog, Verilog and Vera. 5 years experience in verification ... scripting languages Waveform viewing and simulation debugging Post-silicon bringup... more |
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| Feb 26 | Hardware Developer 4 | Oracle | Santa Clara, CA |
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DSP systems. Seeking an experienced Design Verification engineer for a leading edge ... verification IP. Hands on experience with Vera/NTB/SystemVerilog or similar language... more |
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| Feb 26 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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and implementing testplans, developing Vera/SystemVerilog tests and checkers, ... flows and methodologies - Has hand-on verification experience of network traffic... more |
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| Feb 26 | Principal IC Design Engineer | Broadcom | San Jose, CA |
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and implementing testplans, developing Vera/SystemVerilog tests and checkers, ... functional team members, and enhance the verification methodology. Job Requirements :... more |
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| Feb 25 | ASIC Verification Sr. Staff | Conexant | Waltham, MA |
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Oriented Verification languages such as Vera, Specman or System Verilog) required. ... test plans, generating and tracking verification schedules, simulation... more |
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| Feb 25 | Design Verification Engineer - ASIC - Large Scale systems | Cybercoders | New York, NY |
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Verification Engineer - ASIC - Large Scale systems Design Verification Engineer - ... Vera, SystemVerilog, First-Pass, Silicon Success, Complex ASIC Design Verification... more |
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| Feb 25 | Engineer, Principal Design | Broadcom | Austin, TX |
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system modeling and simulation- Development/simulation of RTL hardware implementations ... like System Verilog or System C or Vera.. Write verification test plans.. Run... more |
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| Feb 24 | EDA Core Technology Engineer with HVLs(VERA) knowledge | Massachusetts | |
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HVLs(VERA) knowledge required Maintaining cost reduction and quality improvement ... verification methodologies, test planning, verification environment architectures and... more |
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| Feb 24 | Hardware Developer 4 | Oracle | Spring, TX |
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with 5-7 years of experiences in verification, and modeling- VERA or ... Verilog Design/Verification Digital Chip: Vera Design/Verification Digital Chip: NC... more |
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| Feb 24 | Hardware Developer 4 | Oracle | Spring, TX |
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Verilog Design/Verification Digital Chip: Vera Design/Verification Digital Chip: ... Verilog Design/Verification Digital Chip: Vera Design/Verification Digital Board:... more |
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| Feb 23 | Switch Verification Engineer | Oracle | Santa Clara, CA |
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Title t('12') Switch Verification Engineer t('5') Location t('12') US-Santa ... Individual contributor responsible for the verification of high performance... more |
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| Feb 23 | Switch Verification Engineer | Oracle | Santa Clara, CA |
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Title t('12') Switch Verification Engineer t('5') Location t('12') US-Santa ... Individual contributor responsible for the verification of high performance... more |
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| Feb 23 | Senior EDA Coordinator with HVLs(VERA) knowledge | Massachusetts | |
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HVLs(VERA) knowledge required Maintaining cost reduction and quality improvement ... verification methodologies, test planning, verification environment architectures and... more |
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| Feb 22 | Engineer, Design Verification Test (DVT) | Marvell Technology Group | Austin, TX |
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verification. Perform test development, simulation, debugging, system bring up and ... test benches to work with internal simulation environment. Verify environment... more |
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| Feb 22 | Engineer, ASIC Design | Marvell Technology Group | Santa Clara, CA |
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like System Verilog or System C or Vera. - Able to write verification test ... synthesis, static timing analysis, formal verification. - Understanding of timing... more |
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| Feb 21 | Senior ASIC Design/Verification Engineer | STMicroelectronics | La Jolla, CA |
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RTL Verification ? Experience in developing verification test benches and running simulations at RTL and gate level ? ... scan/BIST insertion and formal verification... more |
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| Feb 21 | Sr. EDA Engineer with HVLs(VERA) knowledge | Massachusetts | |
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HVLs(VERA) knowledge required Maintaining cost reduction and quality improvement ... verification methodologies, test planning, verification environment architectures and... more |
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| Feb 20 | Senior ASIC Design/Verification Engineer | STMicroelectronics | La Jolla, CA |
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RTL Verification ? Experience in developing verification test benches and running simulations at RTL and gate level ? ... scan/BIST insertion and formal verification... more |
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| Feb 19 | Switch Verification Engineer | Oracle | Santa Clara, CA |
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Individual contributor responsible for the verification of high performance ... of direct experience in microprocessor verification. Knowledge of Sparc Assembly... more |
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| Feb 19 | Switch Verification Engineer | Oracle | Santa Clara, CA |
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Individual contributor responsible for the verification of high performance ... of direct experience in microprocessor verification. Knowledge of Sparc Assembly... more |
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| Feb 19 | Hardware Verification Engineer | Oracle | Santa Clara, CA |
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Title t('12') Hardware Verification Engineer t('5') Location t('12') US-Santa ... - BS / MS (preferred) with 5-7 years of experiences in verification, and modeling - VERA... more |
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| Feb 19 | Hardware Verification Engineer | Oracle | Santa Clara, CA |
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Title t('12') Hardware Verification Engineer t('5') Location t('12') US-Santa ... - BS / MS (preferred) with 5-7 years of experiences in verification, and modeling - VERA... more |
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| Feb 19 | Engineer, Design Verification Test (DVT) | Marvell | Austin, TX |
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utilizing constraint based random verification methodologies and industry ... verification. Perform test development, simulation, debugging, system bring up and... more |
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| Feb 19 | Senior EDA Engineer with HVLs(VERA) knowledge | Massachusetts | |
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HVLs(VERA) knowledge required Maintaining cost reduction and quality improvement ... verification methodologies, test planning, verification environment architectures and... more |
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| Feb 19 | Engineer, ASIC Design | Marvell | Santa Clara, CA |
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like System Verilog or System C or Vera. - Able to write verification test ... synthesis, static timing analysis, formal verification. - Understanding of timing... more |
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| Feb 18 | Design Verification Lead - Conexant Systems | Conexant Systems | Waltham, MA |
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test plans, generating and tracking verification schedules, simulation ... and C++ (or Object Oriented Verification languages such as Vera, Specman... more |
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| Feb 17 | Hardware Verification Engineer | Oracle | Santa Clara, CA |
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of Serdes macros and clusters; developing verification checkers, monitors, functional ... - BS / MS (preferred) with 5-7 years of experiences in verification, and modeling - VERA... more |
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| Feb 17 | Hardware Verification Engineer | Oracle | Santa Clara, CA |
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of Serdes macros and clusters; developing verification checkers, monitors, functional ... - BS / MS (preferred) with 5-7 years of experiences in verification, and modeling - VERA... more |
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| Feb 17 | Sales Technical Leader , Advanced Verification Technologies | Cadence Design Systems | San Jose, CA |
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experience in creating Coverage Driven Verification environments utilizing ... Verification Engineer or Design Engineer or Verification AE. Experience in leading... more |
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