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Apr 25 Engineer, Staff Verification Engineer Marvell Technology Group Santa Clara, CA

for motivated and innovative design verification engineer to be part of Marvell's ... Test Bench development, simulations, design verification and debug- Familiarity with... more

Apr 25 Consultant Oxford Global Resources Maynard, MA

client needs a consultant to perform ASIC verification, setting up test benches; ... REQUIRED/MANDATORY SKILLS: ASIC Verification, SystemC or System Verilog... more

Apr 22 ASIC Engineer Seagate Shakopee, MN

excellent understanding of SOC integration, simulation and laboratory troubleshooting. ... Verilog design, and constrained random verification tools such as Vera or Specman.... more

Apr 22 ASIC Engineer Seagate Technology Prior Lake, MN

excellent understanding of SOC integration, simulation and laboratory troubleshooting.? ... Verilog design, and constrained random verification tools such as Vera or Specman.... more

Apr 16 ASIC Verification Engineer Top Echelon Network Sunnyvale, CA

Verification Engineer (Member Technical Staff) Looking for an ASIC verification ... products. Responsibilities include verification of ASICs and systems for... more

Apr 14 Application Engineer Steinman Recruiting Associates San Jose, CA

3+ years ofexperience in functional verification ... ... more

Apr 02 Senior EDA Verification Engineer QUALCOMM Headquarters San Diego, CA

verification.. Strong knowledge of HVLs(VERA), HDLs(Verilog/VHDL/SystemVerilog), ... RTL simulation (ModelSim, VCS, Vera), Formal verification techniques (e.g.... more

Apr 02 LEAD VERIFICATION ENGINEER NVIDIA Corporate Santa Clara, CA

Architect the verification environment and methodology for the world's ... Utilize dynamic simulation, formal verification, emulation, and code coverage-... more

Apr 02 SR. VERIFICATION ENGINEER NVIDIA Corporate Santa Clara, CA

Implement the verification environment and methodology for the world's ... Utilize dynamic simulation, formal verification, emulation, and code coverage-... more

Apr 02 Design Verification Engineer Apple Computer Cupertino, CA

interfaces.Experience with advanced verification techniques such as CRV, VMM, ... Proficient with SystemVerilog/Verilog/Vera/C/C++/Perl See Job Description... more

Apr 02 Engineer, Staff Design Verification Test Marvell Technology Group Longmont, CO

verification environment. Write verification test plans. Execute code ... Extensive experience with SystemVerilog or Vera is required... more

Apr 02 ASIC Verification Engineer - Ready to Hire NOW! FPC (Fortune Personnel Consultants) Maine

of verification projects using high level verification languages Work very closely ... coverage Experience in architecting verification environments and writing test... more

Apr 02 ASIC Verification Engineer - Ready to Hire NOW! FPC (Fortune Personnel Consultants) Rhode Island

of verification projects using high level verification languages Work very closely ... coverage Experience in architecting verification environments and writing test... more

Apr 02 ASIC Verification Engineer - Ready to Hire NOW! FPC (Fortune Personnel Consultants) Massachusetts

of verification projects using high level verification languages Work very closely ... coverage Experience in architecting verification environments and writing test... more

Apr 02 ASIC Verification Engineer - Ready to Hire NOW! FPC (Fortune Personnel Consultants) New Hampshire

of verification projects using high level verification languages Work very closely ... coverage Experience in architecting verification environments and writing test... more

Apr 02 ASIC Verification Engineer - Ready to Hire NOW! FPC (Fortune Personnel Consultants) Vermont

of verification projects using high level verification languages Work very closely ... coverage Experience in architecting verification environments and writing test... more

Apr 02 Staff Logic Design Engineer Marvell Technology Group Santa Clara, CA

and implement verification IP for Ethernetswitches, routers, and SOC ... level verification language (SystemVerilog, Vera, Specman). 4. Solid understanding of... more

Mar 14 Principal ASIC Verification Engineer Top Echelon Network Marlborough, MA

of verification projects using high-level verification languages. You will work very ... coverage ??? Experienced in architecting verification environments and writing test... more

Jan 14 STUDENT INTERN - Hardware Engineering Sun Microsystems Austin, TX

verification. Prior experience doing simulation based verification of small to ... CE, or CSADDITIONAL COURSE WORK:Design Verification EngineeringSun Microsystems... more

More Job Postings from the Web
May 10 Specman or Vera Searchtech Solutions (stecs) San Jose, CA

Full chip verification at 65nm SOC design with Vera / Specman Unix / C++ 5 years... more

May 09 Senior Verification Engineer -SystemVerilog/VERA Innovative LOGIC Portland, OR

methodology and who can handle system verification tasks very efficiently. ... Expertise in verilog, SystemVerilog/VERA (SV, VMM/RVM) Good experience in perl,... more

May 09 Sr. Verification Engineer San Jose, CA

simulation & debug; perform ASIC design & verification; use System Verilog, Verilog, ... Vera languages, PERL, networking protocols, & verification methodologies (like VMM &... more

May 09 Verification Manager Terran Systems Santa Clara, CA

System Verilog, SystemC, Vera, etc) ... (i.e., SystemVerilog, SystemC, Verilog, e, Vera etc) l Various verification methodology(s) l regression test-suite dvlpmt l Creation... more

May 09 HVL Verification Engineer Advanced Engineering Resources Sunnyvale, CA

verification background, andend-to-end verification experience (spec to tapeout)- ... who is very capable with coverage-driven verification and is experienced with... more

May 09 Engineer, Staff Verification Engineer Marvell Semiconductor Santa Clara, CA

Position Description:Looking for motivated and innovative design verification engineer to ... Test Bench development, simulations, design verification and debug- Familiarity with... more

May 09 Digital FPGA Engineer (Entry-level)- Corporate Ramp;D QUALCOMM San Diego, CA

and verification - block design, simulation, and lab verification and ... may be more heavily weighted toward FPGA simulation and lab testing.br... more

May 09 STUDENT INTERN - Hardware Engineering Sun Microsystems Austin, TX

verification. Prior experience doing simulation based verification of small to ... CE, or CSADDITIONAL COURSE WORK:Design Verification EngineeringSun Microsystems... more

May 09 Digital FPGA Engineer (Engineer or Sr. Engineer Level) QUALCOMM San Diego, CA

perl/shell scripting, and VHDL for simulation and synthesis is preferred. Must ... in a fast-paced environment. Experience with Vera and lab test equipment are... more

May 08 Verification Engineer Inmata Solutions San Jose, CA

coverage;- Support for relevant FPGA based verification Qualifications(Required Skills ... coverage, etc.- Hand-on experience with RTL verification with Specman or Vera is... more

May 08 Redback - Senior Verification Engineer Redback San Jose, CA

? Experience in gate level simulations, performance modeling and HW/SW co-verification a ... Vera, C/C and/or System C. ? Strong debugging skills a must. ? Must have good... more

May 08 Engineer, Sr Staff IC Design Verification Broadcom San Jose, CA

Vera tests and checkers, creating reusable verification components, and debugging ... functional team members, and enhance the verification methodology. - This... more

May 08 Intern, Engineering Broadcom San Jose, CA

strength in digital logic design, verification. knowledge of HDL such as ... ASICs in the area of logic design and verification of -- packet processing... more

May 07 RTL Verification Engineer eTech Resources Chandler, AZ

Verification; Verilog; Verilog/VHDL RTL Verification Engineer Assist in RTL ... RTL simulator. Experience in Specman "e" verification language or Vera. Knowledge of... more

May 07 ASIC Design or Verification Engineer Juniper Networks California

Responsibilities include design and verification of ASICs and systems for ... C, C++, SystemC, Perl/shell scripts, and/or Vera. Networking experience is highly... more

May 06 ASIC Verification Engineer (Palo Alto QUALCOMM Palo Alto, CA

in RTL/Behavioral modeling in Verilog EDA Simulation tools (VCS,NCSIM) * Working ... languages including C/C++ * Experienced in Verification of Layer 2 (Ethernet/WLAN)... more

May 06 Verification Product Support Specialist Mentor Graphics Tempe, AZ

Vera and/or PSL and Assertion-Based Verification techniques. ? Experience in ... random directed testing, formal verification and simulation... more

May 06 Product Verification Support Specialist Mentor Graphics Tempe, AZ

Vera and/or PSL and Assertion-Based Verification techniques.** Experience in ... random directed testing, formal verification and simulation... more

May 06 Verification Product Support Specialist Mentor Graphics Arizona

Vera and/or PSL and Assertion-Based Verification techniques. Experience in ... random directed testing, formal verification and simulation... more

May 06 Sr IC Principal Design San Jose, CA

automated, coverage-driven SOC verification environment, where reuse is of high importance. There will be testbench ... across simulation, emulation and silicon bringup 3... more

May 05 ASIC Engineer Xoriant San Jose, CA

Minimum 4-5 years experience in ASIC verification ... verification languages (HVL) such as VERA/SystemC is desirable.Need candidates... more

May 04 Application Engineer - Verification / 50154383 Mentor Graphics Tempe, AZ

customer wins. -Driving adoption of verification products in existing ... on verification methodologies/flows OVM, E, Vera, Specman, VMM, RMM). ,oPrior experience... more

May 02 ASIC Verification Engineer Seagate Technology Massachusetts

are second to none. Responsible for verification of hard disk controller ... tests. Experience with advanced random verification methodologies is highly... more

May 02 ASIC Verification Engineer Seagate Technology Shrewsbury, MA

are second to none. Responsible for verification of hard disk controller ... tests. Experience with advanced random verification methodologies is highly... more

May 02 Staff Verification Engineer (F9-13) San Jose, CA IDT San Jose, CA

Responsibilities Excellent knowledge of vera/SystemVerilog and Verilog ... Create Vera/SystemVerilog test benches and test cases for hardware verification... more

May 02 ASIC Verification Engineer Redback Networks California

• At least 4-10+ years experience ASIC verification ... • Experience in gate level simulations, performance modeling and HW/SW co-verification... more

May 02 Consultant Hirenet Maynard, MA

REQUIRED/MANDATORY SKILLS: ASIC Verification, SystemC or System ... coverage. REQUIRED/MANDATORY SKILLS: ASIC Verification, SystemC or System... more

May 02 CoSimulation Development Engineer Seagate Technology Colorado

to none. Responsible for cosimulation and verification of disc controller, host ... System Verilog). Experience with advanced verification languages (Vera, Specman) is... more

May 02 CoSimulation Development Engineer Seagate Technology Longmont, CO

to none. Responsible for cosimulation and verification of disc controller, host ... System Verilog). Experience with advanced verification languages (Vera, Specman) is... more

May 01 Engineer, Staff Verification Engineer Marvell Santa Clara, CA

Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate ... verification environments, modeling and co-simulation, testvector generation, at the IP... more

May 01 LEAD VERIFICATION ENGINEER Baytech Campbell, CA

VERIFICATION ENGINEER Responsibilities: Architect ... and Vera or Specman e Worked with multiple verification development cycles Demonstrate... more

May 01 ASIC Verification Engineer Juniper Networks Sunnyvale, CA

Juniper is growing! We are looking for ASIC verification engineers to work in a dynamic ... Responsibilities include architecture development and modeling, verification of ASIC and... more

May 01 ASIC DESIGN AND VERIFICATION ENGINEER Terran Systems San Jose, CA

Verification Requirements: Do you have 5-10 years experience working in ASIC ... while utilizing the most current ASIC verification tools available, such as Vera,... more

May 01 Senior FPGA & ASIC Verification Engineer - MediaFLO Tech QUALCOMM San Diego, CA

responsible for designing and developing verification environment components; ... ASIC verification experience should include use of modern verification techniques,... more

May 01 Sr. ASIC Emulation Engineer Oneten Technologies Sunnyvale, CA

subsystem verification, Microprocessor verification, and/or SoC verification. * ... * Knowledge of coverage based verification methodologies or System-Verilog Assertions The... more

May 01 Broadcom Corporation - Intern, Engineering Broadcom San Jose, CA

ASICs in the area of logic design and verification of -- packet processing ... * strength in digital logic design, verification. knowledge of HDL such as... more

May 01 Applications Engineer Netpolarity Cupertino, CA

MX customers by investigating and resolving simulation related issues. Support technical ... verification language such as Synopsys Vera or Verisity Specman-E, Knowledge of... more

May 01 Software Design Engineer STMicroelectronics Longmont, CO

and implementation of software based verification environments. The candidate ... language (Specman/e) to create advanced verification environments. They should be... more

May 01 ASIC Architect & Designer Juniper Networks Westford, MA

and synthesis, working closely with Design Verification engineers to ensure design ... Other desirable skills: SystemC, Vera or equivalentC/C++ Scripting with Perl and/or... more

Apr 30 Senior Verification Engineer Cswitch Santa Clara, CA

Participate in the verification of next-generation high-performance FPGA ... testing, system level verification ? Fluent in Verilog, Vera/Specman, C, C++,... more

Apr 30 Senior ASIC Verification Engineer (Multiple Positions) Terran Systems San Diego, CA

block level as well as chip-level simulation and verification. Key ... verification and debug- Develop functional verification plans - Develop verification... more

Apr 30 Staff Verification Engineer (F9-13) San Jose, CA Integrated Device Technology California

Create Vera/SystemVerilog test benches and test cases for hardware verification ... and simulation techniques, including HVLs (vera/System Verilog) and Verilog. The... more

Apr 30 Verification Lead C2 Microsystems San Jose, CA

ResponsibilitiesLead Verification of blocks and full chip custom ASIC ... and regression suites for design verification Enhance and develop test-bench... more

Apr 30 LEAD VERIFICATION ENGINEER Baytech Solutions Hillsboro, OR

LEAD VERIFICATION ENGINEER Responsibilities: Architect the verification environment ... Vera or Specman ?e? Worked with multiple verification development cycles Demonstrate... more

Apr 30 Core Verification Engineer Denali Software Sunnyvale, CA

verification engineer. Responsible for verification of IP functionality and ... verification test plans System Verilog, Vera, or Specman experience strongly desired... more

Apr 30 Sr., Principle Microprocessor Design Verification Engineers Tsl Associates Austin, TX

Principle Microprocessor Design Verification Engineers!! Join an elite design ... Knowledge in verification methodologies from concept to working silicon ... more

Apr 30 ASIC/SoC Design Engineers: Verification and Synthesis Tsl Associates Austin, TX

digital satellite radio. ASIC/ SoC Design Verification Engineers: Must have a minimum ... tools such as System Verilog, Specman or Vera . Knowledge of VMM, RVM, assertion:SVA,... more

Apr 30 ASIC Verification Engineer (San Diego, Irvine or Los Angeles) Alchemy Irvine, CA

include: • Develop functional test/verification plans, verification modules, ... programming skills • System Verilog, Vera, E, or assertion based verification... more

Apr 30 Seeking a verification engineer for a company in Santa Clara, CA Embedded Resource Group Santa Clara, CA

Verification Engineer to be a key member of the ASIC verification team. ... Vera) is highly desired. Experience with verification of standard memory and host... more

Apr 30 Digital FPGA Engineer (Entry QUALCOMM San Diego, CA

perl/shell scripting, and VHDL for simulation and synthesis is preferred. Must ... in a fast-paced environment. Experience with Vera and lab test equipment are... more

Apr 30 Digital FPGA Engineer (Engineer or Sr. Engineer Level)- Corporate R&D QUALCOMM San Diego, CA

and verification - block design, simulation, and lab verification and debug. ... Additional Skills Experience with Vera and lab test equipment are pluses... more

Apr 30 Staff Logic Design Engineer Marvell Semiconductor Santa Clara, CA

Description:Architect and implement verification IP for Ethernetswitches, ... level verification language (SystemVerilog, Vera, Specman). 4. Solid understanding of... more

Apr 29 Verification Engineer Advanced Engineering Resources Sunnyvale, CA

verification background, andend-to-end verification experience (spec to tapeout) - ... who is very capable with coverage-driven verification and is experienced with... more

Apr 29 RTL Verification Engineer Connexion Systems & Engineering Bloomington, MN

activities including generation of verification plans, generation of ... methods including constrained random verification methods and functional coverage... more

Apr 29 Lead Digital/FPGA Design Engineer General Dynamics Advanced Information Systems Scottsdale, AZ

include concept development, requirements, verification plan, chip architecture, detail ... design, back-annotated timing Gate-level Simulation, Static Timing Analysis,... more

Apr 28 Lead Digital/FPGA Design Engineer General Dynamics Scottsdale, AZ

include concept development, requirements, verification plan, chip architecture, detail ... design, back-annotated timing Gate-level Simulation, Static Timing Analysis,... more

Apr 28 Lead Digital/FPGA Design Engineer Scottsdale, AZ

include concept development, requirements, verification plan, chip architecture, detail ... design, back-annotated timing Gate-level Simulation, Static Timing Analysis,... more

Apr 27 Principal Verification Engineer San Jose, CA

Principal Verification Engineer Verification The industry?s most respected ... Vera tests and checkers, creating reusable verification components, and debugging... more

Apr 27 Lead Digital/FPGA Design Engineer General Dynamics AIS Phoenix, AZ

include concept development, requirements, verification plan, chip architecture, detail ... design, back-annotated timing Gate-level Simulation, Static Timing Analysis,... more

Apr 27 Staff IC Design San Jose, CA

knowledge of ASIC design verification flows and methodologies is ... is strongly preferred.Familiarity with Vera, C++/Specman/SystemC or OOP is highly... more

Apr 25 Engineer, Staff Verification Engineer Marvell Santa Clara, CA

Title: Engineer, Staff Verification Engineer Job Category: Engineering Job Sub ... Test Bench development, simulations, design verification and debug - Familiarity with... more

Apr 25 Denali Software - PCIe Core Verification Engineer Denali Software Sunnyvale, CA

CA Job Description: Responsible for verification of IP functionality and ... verification test plans ? System Verilog, Vera, or Specman experience strongly desired... more

Apr 25 Verification Engineer Modicom Milpitas, CA

Verification Engineer Skills required: * Experience with high level verification ... languages, i.e., SystemVerilog, Vera, TestBuilder, Specman or SystemC. *... more

Apr 25 Synapse Design Automation - Senior Verification Engineer Synapse Design Automation San Jose, CA

5-10 years Requirements: * Fullchip verification testbench and environment ... specs for components and modules in the verification environment (test benches,... more

Apr 25 Denali Software - Verification Lead- PCI-Express Design IP Denali Software Sunnyvale, CA

Responsibilities: * Develop next-generation verification architecture for Denali's ... of customer deliverables * Perform verification reviews with customers and... more

Apr 25 ASIC Verification engineer APN Software Services San Francisco, CA

Please contact Zafar at 510-402-4799 Or mail me at zafar@apninc.com*****************************************************Need strong Vera/RVM skills Need strong Vera/RVM skills more

Apr 25 Emulex - Engineer, Principal ASIC Emulex San Jose, CA

block level & chip level simulation verification, formal verification. Use of ... hands-on experience with state of the art Verification tools such as Vera, Specman,... more

Apr 25 Denali Software - Software Engineer Denali Software Sunnyvale, CA

? Experience in SystemVerilog, Specman, or VERA ? Knowledge of interface protocols ... of professional experience in Verification of ASIC/SoCs, or CAD Tool development... more

Apr 25 Denali Software - Corporate Applications Engineer Denali Software Sunnyvale, CA

technical support of Denali Software's Verification IP. ? Duties will include ... a strong background in verification and verification methodologies, very strong... more

Apr 25 Denali Software - Field Application Engineer Denali Software Sunnyvale, CA

Must have a strong background in verification and verification methodologies ... ? Must understand multiple HDL methodologies with emphasis placed on the verification and... more

Apr 25 Consultant Oxford Global Resources Maynard, MA

client needs a consultant to perform ASIC verification, setting up test benches; ... REQUIRED/MANDATORY SKILLS: ASIC Verification, SystemC or System Verilog... more

Apr 25 Denali Software - Field Application Engineer Denali Software Austin, TX

Must have a strong background in verification and verification methodologies ... ? Must understand multiple HDL methodologies with emphasis placed on the verification and... more

Apr 24 Senior FPGA & ASIC Verification Engineer QUALCOMM San Diego, CA

must possess knowledge of design for verification methodologies. They are ... ASIC verification experience should include use of modern verification techniques,... more

Apr 24 Hardware Design Engineer (Entry Level) Hewlett-Packard Company Roseville, CA

Experience may include: ASIC design and/or verification experience, ideally doing some ... design, ASIC simulation, ASIC post-silicon verification, ASIC microcode, formal... more

Apr 24 Hardware Design Engineer (Entry Level) Hewlett-Packard Roseville, CA

pre-silicon simulation and/or post-silicon verification. * Architect and design ... design, ASIC simulation, ASIC post-silicon verification, ASIC microcode, formal... more

Apr 23 Senior FPGA & ASIC Verification Engineer - MediaFLO Technologies QUALCOMM San Diego, CA

responsible for designing and developing verification environment components; ... ASIC verification experience should include use of modern verification techniques,... more

Apr 23 Western Digital - Senior Staff Engineer, ASIC Verification Western Digital Lake Forest, CA

will include developing SoC verification environment, developing test ... ASIC verification ? Prior experience using Vera, Specman or System Verilog ?... more

Apr 23 Engineer, Principal Design Broadcom Austin, TX

modeling and simulation - Development/simulation of RTL hardware implementations ... like System Verilog or System C or Vera. . Write verification test plans. . Run... more

Apr 23 Western Digital - Sr. Staff Engineer, ASIC Design-Verifica Western Digital Lake Forest, CA

will include developing SoC verification environment, developing test ... ASIC verification. ? Prior experience using Vera, Specman or System Verilog ?... more

Apr 22 Verification Vera / Specman Searchtech Solutions San Jose, CA

with Vera / Specman / VerilogUnix / C++5 years experience Verification, Specman, Vera,... more

Apr 22 ASIC Engineer Seagate Technology Prior Lake, MN

excellent understanding of SOC integration, simulation and laboratory troubleshooting.? ... Verilog design, and constrained random verification tools such as Vera or Specman.... more

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