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Mar 16 ASIC Verification Engineer Intel Austin, TX

These testbenches are implemented using the Specman `e' language. As part of the ... logic simulation, verilog, system verilog, Specman, C . Masters in Electrical or... more

Mar 16 Design Verification Engineer Motorola Austin, TX

BSEE/MSEE preferred Verilog/VHDL SystemVerilog, OVM/Specman preferred ModelSim/ Questa, Cadence IES/Synopsys VCS Experience with Cadence Palladium a plus AMBA/OCP bus experience,... more

Mar 16 Engineering Intern Intel Santa Clara, CA

such as C is required, and logic design, Specman-E understanding would be an added advantage - Exposure to hardware description languages [VHSIC Hardware Description Language... more

Mar 16 Hardware Engineer Intel Hillsboro, OR

areas: VLSI, System Verilog*, VHDL, RTL, Specman*, Gate-level design, Transistor-level design, IA-32 architecture,Power Management (ACPI) knowledge or Object Oriented Programming. more

Mar 16 Sr Staff IC Design Engineer Broadcom Irvine, CA

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

Mar 15 Hardware Engineer Intel Phoenix, AZ

areas: VLSI, System Verilog*, VHDL, RTL, Specman*, Gate-level design, Transistor-level design, IA-32 architecture,Power Management (ACPI) knowledge or Object Oriented Programming. more

Mar 15 Logic Verification Engineer Intel Folsom, CA

team environment - Familiarity with Specman*, gate-level simulation, and Graphics concepts would be an added advantage as would be intern experience in logic design/verification... more

Mar 15 Hardware Engineer Intel Hillsboro, OR

areas: VLSI, System Verilog*, VHDL, RTL, Specman*, Gate-level design, Transistor-level design, IA-32 architecture,Power Management (ACPI) knowledge or Object Oriented Programming. more

Mar 15 Hardware Engineer Intel Sacramento, CA

areas: VLSI, System Verilog*, VHDL, RTL, Specman*, Gate-level design, Transistor-level design, IA-32 architecture,Power Management (ACPI) knowledge or Object Oriented Programming. more

Mar 15 Component Design Engineer Intel Folsom, CA

knowledge of UNIX* tools, Verilog*, Tcl, Specman and Perl scripting - Excellent communication, interpersonal and problem-solving skills - A self-starter with the ability to work... more

Mar 15 Sr Staff IC Design Engineer Broadcom Irvine, CA

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

Mar 15 Sr Staff IC Design Engineer Broadcom Irvine, CA

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

Mar 13 Design Verification Engineer Motorola Austin, TX

BSEE/MSEE preferred Verilog/VHDL SystemVerilog, OVM/Specman preferred ModelSim/ Questa, Cadence IES/Synopsys VCS Experience with Cadence Palladium a plus AMBA/OCP bus experience,... more

Mar 13 Senior ASIC Verification Engineer Xpeerant Longmont, CO

They are using Specman for their test/verification environment ... the primary verification environment is Specman-e . The contract would last 4-6... more

Mar 12 ASIC Verification Engineer Intel Austin, TX

These testbenches are implemented using the Specman `e' language. As part of the ... logic simulation, verilog, system verilog, Specman, C++. Qualifications Masters in... more

Mar 12 Senior Digital ASIC Verification Engineer Fusion408 Santa Clara, CA

tasks. ? At least 2 years experience with Specman constrained random test-bench ? At least 1 year experience with Assertion-Based Verification (ie OVL, PSL, SVA) ? A proven track... more

Mar 12 Design Verification Engineer Motorola Austin, TX

BSEE/MSEE preferred Verilog/VHDL SystemVerilog, OVM/Specman preferred ModelSim/ Questa, Cadence IES/Synopsys VCS Experience with Cadence Palladium a plus AMBA/OCP bus experience,... more

Mar 12 Design Verification Engineer Motorola Austin, TX

BSEE/MSEE preferred Verilog/VHDL SystemVerilog, OVM/Specman preferred ModelSim/ Questa, Cadence IES/Synopsys VCS Experience with Cadence Palladium a plus AMBA/OCP bus experience,... more

Mar 12 Component Design Engineer Intel Folsom, CA

knowledge of UNIX* tools, Verilog*, Tcl, Specman and Perl scripting - Excellent communication, interpersonal and problem-solving skills - A self-starter with the ability to work... more

Mar 12 Design Verification Engineer Motorola Austin, TX

BSEE/MSEE preferred Verilog/VHDL SystemVerilog, OVM/Specman preferred ModelSim/ Questa, Cadence IES/Synopsys VCS Experience with Cadence Palladium a plus AMBA/OCP bus experience,... more

Mar 12 Hardware Engineer Intel Hillsboro, OR

areas: VLSI, System Verilog*, VHDL, RTL, Specman*, Gate-level design, Transistor-level design, IA-32 architecture,Power Management (ACPI) knowledge or Object Oriented Programming. more

Mar 11 Senior ASIC Verification Engineer ? Video Modicom San Jose, CA

Desired:--+2 years experience with Specman constrained random test-bench knowledge --+1 year experience with Assertion-Based Verification (SVA, OVL, PSL) --Strong appreciation for... more

Mar 11 Senior ASIC Verification Engineer ? Video Modicom San Jose, CA

Desired: --+2 years experience with Specman constrained random test-bench knowledge --+1 year experience with Assertion-Based Verification (SVA, OVL, PSL) --Strong appreciation... more

Mar 11 Senior ASIC Verification Engineer Digital Modicom Sunnyvale, CA

Strongly Desired * +2 years experience with Specman constrained random test-bench knowledge * +1 year experience with Assertion-Based Verification (SVA, OVL, PSL) * Strong... more

Mar 11 Senior Digital ASIC Verification Engineer Fusion408 Santa Clara, CA

tasks. ? At least 2 years experience with Specman constrained random test-bench ? At least 1 year experience with Assertion-Based Verification (ie OVL, PSL, SVA) ? A proven track... more

Mar 10 Field Application Engineers (FAE) [Verification EXp] Inmata Solutions Mountain View, CA

skills * Working knowledge of VHDL, Specman, Vera, System C is a plus * Knowledge of protocols such as PCI-E, USB, 10 Gig is plus * Experience with memory solutions is a plus 2,... more

Mar 10 Staff Design Verification Engineer SiRF Technology San Jose, CA

using SystemVerilog, SystemC, Vera or Specman. * Strong expertise in writing test benches - BFM, monitors, scoreboard/checker, code coverage & functional coverage. * Must be a... more

Mar 08 Verification Engineer I & I Software Allentown, PA

tests and debugging those *Experienced in Specman *RTL design knowledge *Experience with IC simulator tool (mentor Questa) *Experience in source code control environment like... more

Mar 07 ASIC Verification Sr. Staff Conexant Waltham, MA

Verification languages such as Vera, Specman or System Verilog) required. Experience with OVM/VVM, Verilog Assertions, Functional coverage, UNIX/Linux strongly desirable. more

Mar 06 ASIC Functional Verification Architect CAE Recruiters San Jose, CA

?Working knowledge of VHDL, SystemVerilog, Specman, Vera, System C ?Knowledge of protocols such as PCI-E, USB, 10 Gig Contact: John Visconti at jv@cae-jobs.com or 978-667-6680 CAE... more

Mar 06 ASIC Functional Verification Architect CAE Recruiters San Jose, CA

Verilog simulation Synopsys DesignCompiler, Synopsys PrimeTime, perl, TCL and UNIX shell scripting ?Working knowledge of VHDL, SystemVerilog, Specman, Vera, System C ?Knowledge... more

Mar 05 Verification Engineers Koa Networks San Jose, CA

programming skills SystemVerilog Vera Specman computer architecture PCIe ... language such as SystemVerilog, Vera, or Specman. ** Familiar with verification reuse... more

Mar 05 ASIC Verification Engineer Koa Networks San Jose, CA

verilog, verilog, vmm, ovm, perl, vera, specman ======================================================================= PLEASE SEND ALL RESUMES AS WORD DOC. TO... more

Mar 04 Design Verification Engineer QUALCOMM Santa Clara, CA

ramming skills * Strong verification skills: test planning, problem solving, debug, adversarial testing * Strong working knowledge of HVLs: VERA/e-Specman * Verilog or VHDL,... more

Mar 03 Verification Engineers Koa Networks San Jose, CA

programming skills SystemVerilog Vera Specman computer architecture PCIe ... language such as SystemVerilog, Vera, or Specman. ** Familiar with verification reuse... more

Mar 03 ASIC Verification Engineer Koa Networks San Jose, CA

verilog, verilog, vmm, ovm, perl, vera, specman ======================================================================= PLEASE SEND ALL RESUMES AS WORD DOC. TO... more

Feb 26 Staff Engineer - Verification Western Digital Longmont, CO

debug and integrate designs * Create Specman based testbench to control logic Blocks of RTL * Develop software to control ASIC designs in simulation * Develop verification... more

Feb 25 RTL Verification Engineers Miracle Software Allentown, PA

tests and debugging those Experienced in Specman - RTL design knowledge - Experience with IC simulator tool (mentor Questa) - Experience in source code control environment like... more

Feb 25 ASIC Verification Sr. Staff Conexant Waltham, MA

Verification languages such as Vera, Specman or System Verilog) required. Experience with OVM/VVM, Verilog Assertions, Functional coverage, UNIX/Linux strongly desirable. more

Feb 22 Engineer, Design Verification Test (DVT) Marvell Technology Group Austin, TX

ality of the design utilizing object oriented high level verification languages and methodologies such as System Verilog, C++, Vera, or Specman E language. Verify code coverage... more

Feb 22 Sr Staff IC Design Engineer Broadcom Irvine, CA

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

Feb 20 Senior Verification Engineer (RTL Verification) Qthink San Diego, CA

or all of the following: 1. SAS 2. SATA 3. Specman 4. e Language 5. Incisive 6. RTL Verification 7. Hard Disk Drive 8. Read Write Channel 9. ARM Subsystem. Prefer at least 5 years... more

Feb 20 Logic Verification Engineer Intel Folsom, CA

team environment - Familiarity with Specman* and Graphics concepts, and experience with gate-level simulation would be an added advantage Job Category : Engineering Primary... more

Feb 19 Engineer, Design Verification Test (DVT) Marvell Austin, TX

methodologies: C++/System Verilog/Vera/Specman E language; and at least one of the ... such as System Verilog, C++, Vera, or Specman E language. Verify code coverage and... more

Feb 18 Application Engineer Breker Verificaiton Systems San Jose, CA

random methodologies (System Verilog, SpecMan VCS), excellent communication skills and a desire to work with customers to advance the adoption of Breker's scenario modeling... more

Feb 18 Design Verification Lead - Conexant Systems Conexant Systems Waltham, MA

Verification languages such as Vera, Specman or System Verilog) required. Experience with OVM/VVM, Verilog Assertions, Functional coverage, UNIX/Linux strongly desirable. more

Feb 18 Senior ASIC Verification Engineer Xpeerant Colorado

They are using Specman for their test/verification environment ... the primary verification environment is Specman-e . The contract would last 4-6... more

Feb 17 Sales Technical Leader , Advanced Verification Technologies Cadence Design Systems San Jose, CA

environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ ... Languages: System Verilog + Verilog, VHDL, Specman, Vera, C++, or SystemC... more

Feb 17 Logic Verification Engineer Intel Folsom, CA

lls - Ability to deliver high-quality output against deadlines - Ability to work effectively in a cross-site team environment - Familiarity with Specman* and Graphics concepts,... more

Feb 14 Senior ASIC/VLSI design Engineer (frontend) Cross Creek Systems Campbell, CA

using modern verification techniques (e.g. Specman, assertion-based verification, formal verification model checking, etc. ) Experience in model checking is an advantage Embedded... more

Feb 14 Senior Verification Engineer Cross Creek Systems Campbell, CA

experience with Specman is a major advantage. Must be highly motivated and skillful at solving difficult technical problems Must have excellent communication skills and the... more

Feb 12 Sales Technical Leader , Advanced Verification Technologies Cadence Design Systems San Jose, CA

environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ ... System Verilog + Verilog, VHDL, Specman, Vera, C++, or... more

Feb 12 Staff Design Verification Engineer SiRF Technology San Jose, CA

using SystemVerilog, SystemC, Vera or Specman. Strong expertise in writing test benches - BFM, monitors, scoreboard/checker, code coverage & functional coverage. Must be a team... more

Feb 12 Principle IC Design Engineer Broadcom Irvine, CA

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

Feb 11 Principle IC Design Engineer Broadcom Irvine, CA

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

Feb 10 Staff Design Verification Engineer SiRF Technology San Jose, CA

using SystemVerilog, SystemC, Vera or Specman. Strong expertise in writing test benches - BFM, monitors, scoreboard/checker, code coverage & functional coverage. Must be a team... more

Feb 10 Component Design Engineer Intel Folsom, CA

knowledge of UNIX* tools, Verilog*, Tcl, Specman and Perl scripting - Excellent communication, interpersonal and problem-solving skills - A self-starter with the ability to work... more

Feb 09 Staff Design Verification Engineer SiRF Technology San Jose, CA

using SystemVerilog, SystemC, Vera or Specman. * Strong expertise in writing test benches - BFM, monitors, scoreboard/checker, code coverage & functional coverage. * Must be a... more

Feb 09 Hardware Design Verification Engineer - Modem Comm QUALCOMM San Diego, CA

of HVLs: SystemVerilog TB, VERA, or e-Specman* Verilog or VHDL, C/C++, Tcl/Perl/shell-scriptingResponsibilities Education Requirements Required: Bachelor's, Computer Engineering... more

Feb 09 Design Verification Engineer - Santa Clara Office QUALCOMM Santa Clara, CA

Strong working knowledge of HVLs: VERA/e-Specman* Verilog or VHDL, C/C++, Tcl/Perl/shell-scriptingEducation Requirements BS/MS/PhD in Electrical Engineering or Computer Science... more

Feb 09 Hardware Design Verification Engineer - All Levels QUALCOMM San Diego, CA

Strong working knowledge of HVLs: VERA/e-Specman* Verilog or VHDL, C/C++, Tcl/Perl/shell-scriptingResponsibilities Education Requirements BS/MS/PhD in Electrical Engineering or... more

Feb 09 Director/Principal Engineer of Design Verification QUALCOMM San Diego, CA

in SystemVerilog, Vera, Verisity/Specman and/or SystemC preferred.You should have experience leading dynamic, effective teams and as such, excellent organization and time and... more

Feb 09 Design Verification Engineer (ASIC, Vera, C++) - C QUALCOMM San Diego, CA

Must be skilled in Vera, Specman-E or, C++/OOP, and have a strong background in data structures and algorithms. Hands-on chip verification experience is required. Chip design... more

Feb 09 Staff Design Verification Engineer SiRF Technology San Jose, CA

using SystemVerilog, SystemC, Vera or Specman. * Strong expertise in writing test benches - BFM, monitors, scoreboard/checker, code coverage & functional coverage. * Must be a... more

Feb 06 Sr Sales Technical Leader Cadence Design Systems San Diego, CA

environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ ... Languages: System Verilog + Verilog, VHDL, Specman, Vera, C++, or SystemC... more

Feb 05 Senior Engineer, ASIC Design/Verification Marvell Santa Clara, CA

Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate must show a strong knowledge in the development of chip verification environments and a proven track... more

Feb 03 Principal Verification Engineer Broadcom Austin, TX

languages/environments like Vera, Specman/e is a big plus.* Familiarity with constrained random and assertion based verification is preferred* Understanding of simulation,... more

Jan 31 Principal IC Design Engineer Broadcom Irvine, CA

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation* DSP function hardware implementation such as Digital Filer,... more

Jan 22 Principal IC Design Engineer Broadcom Irvine, CA

tools like SystemVerilog, System C or Specman is desirable. MATLAB and C/C++ based system simulation and evaluation DSP function hardware implementation such as Digital Filer,... more

Jan 20 Validation Engineer Intel Folsom, CA

or Intel's Hardware Description Language (iHDL)] would be an added advantage - Validation and familiarity of industry standard tools such as Specman* and Debussy* would be an... more

Jan 19 Design Verification Engineer - Santa Clara Office QUALCOMM Campbell, CA

* Strong working knowledge of HVLs: VERA/e-Specman * Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting Additional Skills Education Requirements BS/MS/PhD in Electrical Engineering... more

Jan 16 Applications Eng Manager / 50226357 Mentor Graphics San Jose, CA

using ModelSim, NCSim, VCS, Verisity Specman or VERA - Knowledge of Transaction Level Modeling and methodologies would be beneficial. - Previous experience with... more

Jan 15 Design Verification Engineer - Santa Clara Office QUALCOMM Santa Clara, CA

s programming skills Strong verification skills: test planning, problem solving, debug, adversarial testing Strong working knowledge of HVLs: VERA/e-Specman Verilog or VHDL,... more

Jan 10 Staff Verification Engineer Silicon Image Sunnyvale, CA

languages like System Verilog (OVM, VMM), Specman, C/PLI etc.- Must be proficient in Verilog (System Verilog preferred).- Proficiency in scripting language like Perl, Tcl/Tk,... more

Jan 09 Staff Verification Engineer Silicon Image Sunnyvale, CA

languages like System Verilog (OVM, VMM), Specman, C/PLI etc. - Must be proficient in Verilog (System Verilog preferred). - Proficiency in scripting language like Perl, Tcl/Tk,... more

Jan 04 HARDWARE VERIFICATION LEAD George Olivas San Jose, CA

and Verification languages: Verilog, VHDL, Specman e, SystemVerilog, Vera. - Other relevant languages: SystemC, C, Perl, makefile generation. - Hardware Verification Methodologies... more

Dec 29 Staff Design Engineer Silicon Image Sunnyvale, CA

in verification languages (System Verilog, Specman, C/PLI etc) is a plus - Good understanding of overall ASIC flow - Good written and oral communication skills. - Good team player... more

Dec 26 Engineering Intern Intel Santa Clara, CA

such as C is required, and logic design, Specman-E understanding would be an added advantage - Exposure to hardware description languages [VHSIC Hardware Description Language... more

Dec 17 Engineering Intern Intel Santa Clara, CA

such as C is required, and logic design, Specman-E understanding would be an added advantage - Exposure to hardware description languages [VHSIC Hardware Description Language... more

Dec 10 Sr. Staff Verification Engineer Silicom Image Sunnyvale, CA

level languages like System Verilog, C/PLI, Specman, Perl. Build new components and ... languages like System Verilog (OVM, VMM), Specman, C/PLI etc. - Must be proficient in... more

Dec 10 Staff Verification Engineer Silicom Image Sunnyvale, CA

languages like System Verilog (OVM, VMM), Specman, C/PLI etc. - Must be proficient in Verilog (System Verilog preferred). - Proficiency in scripting language like Perl, Tcl/Tk,... more

Dec 10 Staff Design Engineer Silicom Image Sunnyvale, CA

in verification languages (System Verilog, Specman, C/PLI etc) is a plus - Good understanding of overall ASIC flow - Good written and oral communication skills. - Good team player... more

Nov 06 Field Applications Engineer Denali Software Sunnyvale, CA

Strong Plus: * Working knowledge of VHDL, Specman, Vera, System C * Knowledge of protocols such as PCI-E, USB, 10 Gig * Experience with memory solutions * MSEE Position is open in... more

Oct 25 Sr. Staff Verification Engineer Silicon Image Sunnyvale, CA

level languages like System Verilog, C/PLI, Specman, Perl. Build new components and ... languages like System Verilog (OVM, VMM), Specman, C/PLI etc. - Must be proficient in... more

Oct 25 Staff Verification Engineer Silicon Image Sunnyvale, CA

languages like System Verilog (OVM, VMM), Specman, C/PLI etc. - Must be proficient in Verilog (System Verilog preferred). - Proficiency in scripting language like Perl, Tcl/Tk,... more

Oct 25 Staff Design Engineer Silicon Image Sunnyvale, CA

in verification languages (System Verilog, Specman, C/PLI etc) is a plus - Good understanding of overall ASIC flow - Good written and oral communication skills. - Good team player... more

Oct 22 Technical Leader , Advanced Verification Technologies Cadence Design San Diego, CA

environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ ... System Verilog + Verilog, VHDL, Specman, Vera, C++, or SystemCMethodologies:... more

Oct 21 Technical Leader , Advanced Verification Technologies Cadence Design San Diego, CA

environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ ... Languages: System Verilog + Verilog, VHDL, Specman, Vera, C++, or SystemC... more

Oct 19 HW Validation Engineer (Emulation and post-Si) QUALCOMM San Diego, CA

Design verification, ideally using Vera or Specman. Familiarity with VLSI design in HDL. Familiarity with board-level layout. High initiative - we are often doing things not done... more

Sep 18 Lead Services AE Cadence Design Systems China, TX

is a must - Experience with SystemVerilog/Specman/SystemC is a big advantage - SOC HW/SW codesign and coverification is a plus - Experience with formal verification tech with... more

Aug 03 HW Validation Engineer (Emulation and post QUALCOMM San Diego, CA

verification, ideally using Vera or Specman. Familiarity with VLSI design in HDL. Familiarity with board-level layout. High initiative - we are often doing things not done... more

Jul 28 Hardware Design Verification Engineer QUALCOMM San Diego, CA

ming skills * Strong verification skills: test planning, problem solving, debug, adversarial testing * Strong working knowledge of HVLs: VERA/e-Specman * Verilog or VHDL,... more

May 28 ASIC DESIGN VERIFICATION, VERA San Jose, CA

coverage and functional coverage goals Requirements: Expertise in Verilog and/or VHDL, Proficiency in VERA, C/C++, Cadence and Synopsys tools, Specman, testplan. PhD desired. more

May 28 ASIC DESIGN VERIFICATION, VERA New York, NY

coverage and functional coverage goals Requirements: Expertise in Verilog and/or VHDL, Proficiency in VERA, C/C++, Cadence and Synopsys tools, Specman, testplan. PhD desired. more