These testbenches are implemented using the Specman `e' language. As part of the ... logic simulation, verilog, system verilog, Specman, C . Masters in Electrical or... more

such as C is required, and logic design, Specman-E understanding would be an added advantage - Exposure to hardware description languages [VHSIC Hardware Description Language... more

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

team environment - Familiarity with Specman*, gate-level simulation, and Graphics concepts would be an added advantage as would be intern experience in logic design/verification... more

areas: VLSI, System Verilog*, VHDL, RTL, Specman*, Gate-level design, Transistor-level design, IA-32 architecture,Power Management (ACPI) knowledge or Object Oriented Programming. more

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

BSEE/MSEE preferred Verilog/VHDL SystemVerilog, OVM/Specman preferred ModelSim/ Questa, Cadence IES/Synopsys VCS Experience with Cadence Palladium a plus AMBA/OCP bus experience,... more

These testbenches are implemented using the Specman `e' language. As part of the ... logic simulation, verilog, system verilog, Specman, C++. Qualifications Masters in... more

BSEE/MSEE preferred Verilog/VHDL SystemVerilog, OVM/Specman preferred ModelSim/ Questa, Cadence IES/Synopsys VCS Experience with Cadence Palladium a plus AMBA/OCP bus experience,... more

knowledge of UNIX* tools, Verilog*, Tcl, Specman and Perl scripting - Excellent communication, interpersonal and problem-solving skills - A self-starter with the ability to work... more

areas: VLSI, System Verilog*, VHDL, RTL, Specman*, Gate-level design, Transistor-level design, IA-32 architecture,Power Management (ACPI) knowledge or Object Oriented Programming. more

Desired: --+2 years experience with Specman constrained random test-bench knowledge --+1 year experience with Assertion-Based Verification (SVA, OVL, PSL) --Strong appreciation... more

tasks. ? At least 2 years experience with Specman constrained random test-bench ? At least 1 year experience with Assertion-Based Verification (ie OVL, PSL, SVA) ? A proven track... more

using SystemVerilog, SystemC, Vera or Specman. * Strong expertise in writing test benches - BFM, monitors, scoreboard/checker, code coverage & functional coverage. * Must be a... more

Verification languages such as Vera, Specman or System Verilog) required. Experience with OVM/VVM, Verilog Assertions, Functional coverage, UNIX/Linux strongly desirable. more

Verilog simulation Synopsys DesignCompiler, Synopsys PrimeTime, perl, TCL and UNIX shell scripting ?Working knowledge of VHDL, SystemVerilog, Specman, Vera, System C ?Knowledge... more

verilog, verilog, vmm, ovm, perl, vera, specman ======================================================================= PLEASE SEND ALL RESUMES AS WORD DOC. TO... more

programming skills SystemVerilog Vera Specman computer architecture PCIe ... language such as SystemVerilog, Vera, or Specman. ** Familiar with verification reuse... more

debug and integrate designs * Create Specman based testbench to control logic Blocks of RTL * Develop software to control ASIC designs in simulation * Develop verification... more

Verification languages such as Vera, Specman or System Verilog) required. Experience with OVM/VVM, Verilog Assertions, Functional coverage, UNIX/Linux strongly desirable. more

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

team environment - Familiarity with Specman* and Graphics concepts, and experience with gate-level simulation would be an added advantage Job Category : Engineering Primary... more

random methodologies (System Verilog, SpecMan VCS), excellent communication skills and a desire to work with customers to advance the adoption of Breker's scenario modeling... more

They are using Specman for their test/verification environment ... the primary verification environment is Specman-e . The contract would last 4-6... more

lls - Ability to deliver high-quality output against deadlines - Ability to work effectively in a cross-site team environment - Familiarity with Specman* and Graphics concepts,... more

experience with Specman is a major advantage. Must be highly motivated and skillful at solving difficult technical problems Must have excellent communication skills and the... more

using SystemVerilog, SystemC, Vera or Specman. Strong expertise in writing test benches - BFM, monitors, scoreboard/checker, code coverage & functional coverage. Must be a team... more

tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation such as Digital Filer,... more

knowledge of UNIX* tools, Verilog*, Tcl, Specman and Perl scripting - Excellent communication, interpersonal and problem-solving skills - A self-starter with the ability to work... more

of HVLs: SystemVerilog TB, VERA, or e-Specman* Verilog or VHDL, C/C++, Tcl/Perl/shell-scriptingResponsibilities Education Requirements Required: Bachelor's, Computer Engineering... more

Strong working knowledge of HVLs: VERA/e-Specman* Verilog or VHDL, C/C++, Tcl/Perl/shell-scriptingResponsibilities Education Requirements BS/MS/PhD in Electrical Engineering or... more

Must be skilled in Vera, Specman-E or, C++/OOP, and have a strong background in data structures and algorithms. Hands-on chip verification experience is required. Chip design... more

environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ ... Languages: System Verilog + Verilog, VHDL, Specman, Vera, C++, or SystemC... more

languages/environments like Vera, Specman/e is a big plus.* Familiarity with constrained random and assertion based verification is preferred* Understanding of simulation,... more

tools like SystemVerilog, System C or Specman is desirable. MATLAB and C/C++ based system simulation and evaluation DSP function hardware implementation such as Digital Filer,... more

* Strong working knowledge of HVLs: VERA/e-Specman * Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting Additional Skills Education Requirements BS/MS/PhD in Electrical Engineering... more

s programming skills Strong verification skills: test planning, problem solving, debug, adversarial testing Strong working knowledge of HVLs: VERA/e-Specman Verilog or VHDL,... more

languages like System Verilog (OVM, VMM), Specman, C/PLI etc. - Must be proficient in Verilog (System Verilog preferred). - Proficiency in scripting language like Perl, Tcl/Tk,... more

in verification languages (System Verilog, Specman, C/PLI etc) is a plus - Good understanding of overall ASIC flow - Good written and oral communication skills. - Good team player... more

such as C is required, and logic design, Specman-E understanding would be an added advantage - Exposure to hardware description languages [VHSIC Hardware Description Language... more

languages like System Verilog (OVM, VMM), Specman, C/PLI etc. - Must be proficient in Verilog (System Verilog preferred). - Proficiency in scripting language like Perl, Tcl/Tk,... more

Strong Plus: * Working knowledge of VHDL, Specman, Vera, System C * Knowledge of protocols such as PCI-E, USB, 10 Gig * Experience with memory solutions * MSEE Position is open in... more

languages like System Verilog (OVM, VMM), Specman, C/PLI etc. - Must be proficient in Verilog (System Verilog preferred). - Proficiency in scripting language like Perl, Tcl/Tk,... more

environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ ... System Verilog + Verilog, VHDL, Specman, Vera, C++, or SystemCMethodologies:... more

Design verification, ideally using Vera or Specman. Familiarity with VLSI design in HDL. Familiarity with board-level layout. High initiative - we are often doing things not done... more

verification, ideally using Vera or Specman. Familiarity with VLSI design in HDL. Familiarity with board-level layout. High initiative - we are often doing things not done... more

coverage and functional coverage goals Requirements: Expertise in Verilog and/or VHDL, Proficiency in VERA, C/C++, Cadence and Synopsys tools, Specman, testplan. PhD desired. more