BSEE/MSEE with 2+ years experience in logic design and verification. Knowledge of Verilog and EDA tools such as Synopsys DesignCompiler & PrimeTime is required. Familiar with storage & other protocols (SATA/SAS/FiberChannel/PCIe) is desirable. Good communication skill and the ability to work well in a team.

BSEE/MSEE with 2+ years experience in logic design and verification. Knowledge of Verilog and EDA tools such as Synopsys DesignCompiler & PrimeTime is required. Familiar with storage & other protocols (SATA/SAS/FiberChannel/PCIe) is desirable. Good communication skill and the ability to work well in a team.