Senior Chip Integration Engineer
This position will require knowledge and experience in dealing with chip-level integration issues like High-speed interface IP specification, IP vendor design interaction, IP qualification and integration, Power analysis, Clock-tree design, ESD, signal integrity analysis, IR drop, EM analysis, interface between package/substrate design and physical design for bump-allocation.

This position also involves working with vendors to complete and the physical design of the chips, following by chip bring up, characterization and productization.

The candidate must be knowledgeable enough to make the right design trade-offs and make appropriate recommendations to the IP design and PD teams and follow-through.
The background of the successful candidate for this position will include the following characteristics:

1. BSE/MSEE and 7+ years of ASIC Specification, Design, and Implementation.
2. System on Chip design experience is required. Northbridge/chipset experience is a plus.
3. Proficient in Verilog.
4. Understanding of pcb level design and system manufacturing preferred.
5. Analog design and spice level simulation experience is a plus
6. Familiarity with test integration, memory BIST architecture and JTAG/1149.1 is preferred.
7. Chip bring-up experience is a plus.
8. Candidate must possess good communication skills and the ability to work well in a team

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